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  • Different “SoC” ASICs in 90nm – 180nm Fab Technology
  • Hardware IPs
    Single or Multiple CPU Core
    - Single or Multiple DSP Core
    - DDR2 Controller
    - PCI Express
    Ethernet MAC
    - Various Peripheral IP Cores
  • Developed several Flash Memory models in Verilog and VHDL
  • Developed customer-specific RTL IP’s
    - For efficient use of bus with multi-initiator environment
    - Wrapper or Bridging Logic for designing-in 3rd-Party or Customer supplied IP’s
    - Test and Verification Environment
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